CMOS-Compatible Strain Engineering in Monolayer Semiconductor Transistors

Academic Background

With the continuous advancement of semiconductor technology, two-dimensional (2D) materials have garnered significant attention for their atomic-level thinness, which makes them ideal for high-density, low-power electronic devices. Among them, transition metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS₂), stand out due to their exceptional electrical properties, positioning them as promising candidates for future transistor channels. However, despite these remarkable laboratory results, a major challenge lies in integrating 2D materials into existing complementary metal-oxide-semiconductor (CMOS) technology.

Strain engineering has played a pivotal role in modern silicon-based electronics, significantly enhancing carrier mobility by altering material band structures. Introduced in the 1990s, strain engineering achieved commercial success in the early 2000s. Yet, implementing similar strain effects in 2D materials — particularly in a CMOS-compatible manner — remains an unresolved issue. This study addresses this gap by exploring how a CMOS-compatible approach on silicon substrates can apply strain to monolayer MoS₂ transistors, thereby boosting their performance.

Paper Information

This research was conducted by Marc Jaikissoon, Çağıl Köroğlu, Jerry A. Yang, Kathryn Neilson, Krishna C. Saraswat, and Eric Pop, all affiliated with Stanford University’s departments of Electrical Engineering, Materials Science & Engineering, and Applied Physics. Published in Nature Electronics in October 2024, the article is titled “CMOS-Compatible Strain Engineering for Monolayer Semiconductor Transistors.”

Research Process and Results

1. Principles of Strain Engineering and Experimental Design

The core concept of this study is to enhance the electrical performance of monolayer MoS₂ transistors by applying controllable strain. To achieve this, the researchers used silicon nitride (SiNₓ) as the strain-inducing layer, deposited via plasma-enhanced chemical vapor deposition (PECVD) at a low temperature of 350°C. The low thermal budget ensures compatibility with CMOS processes and allows the technique to be implemented on silicon substrates.

1.1 Monolayer MoS₂ Fabrication and Device Architecture

Monolayer MoS₂ was synthesized through chemical vapor deposition (CVD) on a 90 nm SiO₂/p⁺⁺ silicon substrate. Gold (Au) contacts (50 nm) were then deposited onto the MoS₂ via electron-beam evaporation. To protect MoS₂ from possible damage during SiNₓ deposition, a 1.5 nm aluminum (Al) layer was first deposited, followed by 10 nm of aluminum oxide (Al₂O₃) through atomic layer deposition (ALD).

1.2 SiNₓ Strain Layer Deposition and Stress Calibration

The SiNₓ strain layer was deposited at 350°C using PECVD, with stress tunable by adjusting deposition parameters, such as the NH₃:SiH₄ gas ratio. Higher NH₃:SiH₄ ratios resulted in tensile stress, while lower ratios led to compressive stress. The study focused on high-tensile-stressed SiNₓ films (~600 MPa) to analyze their impact on MoS₂ transistors.

2. Effects of Strain on Transistor Performance

2.1 Enhanced Performance in Back-Gated (BG) Transistors

The effects of strain were first studied in back-gated (BG) transistors. By varying transistor dimensions (channel and contact lengths ranging from 1 µm to 200 nm), the researchers found that applying a high-tensile-stressed SiNₓ layer significantly increased on-state current (Iₒₙ). Specifically, the median Iₒₙ for 200 nm devices improved by 60% after strain was introduced, whereas 1 µm devices only experienced a 14% enhancement. These results highlight that strain effects are more pronounced in nanoscale devices.

2.2 Enhanced Performance in Dual-Gated (DG) Transistors

To further validate the strain engineering approach, dual-gated (DG) transistors were fabricated. Results showed that for devices with dimensions of 200 nm, Iₒₙ increased by 45% after applying a high-tensile-stressed SiNₓ layer, whereas for devices with dimensions of 2 µm, the increase was minimal. This consistency with BG results reinforces the conclusion that strain effects are most effective in nanoscale devices.

3. Finite Element Simulation of Strain Distribution

To understand how strain improves transistor performance, the researchers conducted finite element simulations to model strain distribution across devices of varying dimensions. These simulations revealed that the tensile stress of the SiNₓ layer induces a complex, non-uniform strain profile, reducing the Schottky barrier height (SBH) in contact regions and thereby lowering contact resistance. This mechanism serves as the primary reason for performance improvements observed in the strained transistors.

Conclusions and Significance

This work successfully demonstrates a CMOS-compatible strain engineering approach that significantly enhances the performance of monolayer MoS₂ transistors. Key findings include:

• Performance Improvements: Nanoscale transistors (200 nm) showed up to a 60% increase in Iₒₙ after applying high-tensile-stressed SiNₓ, reaching a saturation current of 488 µA/µm at a 400 nm contact pitch.
• CMOS Compatibility: The stress-inducing process uses a low-temperature PECVD method compatible with existing CMOS fabrication techniques.
• Nanoscale Effect: Strain-induced performance enhancements are highly pronounced in nanoscale transistors, making this technique particularly relevant for future device miniaturization.

Study Highlights

1. CMOS Compatibility: The proposed strain-engineering method integrates seamlessly with CMOS processes, enabling practical applications of 2D materials in the semiconductor industry.
2. Nanoscale Effectiveness: The study underscores the pronounced effectiveness of strain engineering in devices with reduced dimensions, aligning with trends in semiconductor scaling.
3. Material Versatility: While the study focuses on MoS₂, the technique can be extended to other 2D materials, such as tungsten diselenide (WSe₂), paving the way for further exploration.

Future Outlook

The findings of this research open new avenues for integrating 2D materials into semiconductor devices. As transistor dimensions continue to shrink, strain engineering is expected to play an increasingly significant role. Moreover, the method could be adapted to other 2D materials, broadening its applicability across the semiconductor landscape.

Through this study, it becomes evident that strain engineering has immense potential to improve the performance of 2D material-based transistors. With continued advancements, this approach could become a cornerstone technique in next-generation semiconductor technology, pushing the boundaries of high-performance electronics.