Scaled Vertical-Nanowire Heterojunction Tunnelling Transistors with Extreme Quantum Confinement

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vertical nanowire heterojunction tunnelling transistor quantum confinement low-voltage operation high drive current subthreshold swing

A Breakthrough in Achieving High-Performance, Energy-Efficient Electronics Using Vertically Scaled Nanowire Heterojunction Tunneling Transistors under Extreme Quantum Confinement

Academic Background

The rapid development of data-driven computing and artificial intelligence has set higher demands for energy-efficient electronic devices. However, further scaling of conventional silicon-based complementary metal-oxide-semiconductor (CMOS) technology is increasingly challenging due to physical limitations. These limits include the minimum gate length imposed by short-channel effects and direct source-to-drain tunneling, as well as the 60 mV/dec subthreshold swing (SS) thermal limit at room temperature, dictated by Fermi-Dirac electron statistics, also known as the “Boltzmann tyranny.” Consequently, researchers are seeking innovative transistor architectures to meet the needs of next-generation high-performance computing for low power consumption, high drive current, and small footprint.

Among the new designs, tunneling field-effect transistors (TFETs) have garnered significant attention due to their potential for achieving deep sub-thermal switching and high drive current. Theoretically, TFETs based on broken-band heterojunction structures could achieve sub-60 mV/dec subthreshold swings and drive currents exceeding 300 µA/µm at room temperature. However, until now, experimental efforts have not successfully integrated these two key performance metrics into a single device.

Paper Source

This study, written by Yanjie Shao and Jesús A. del Alamo from the Massachusetts Institute of Technology (MIT), alongside Marco Pala from Université Paris-Saclay in France, David Esseni from the University of Udine in Italy, and Hao Tang and Ju Li from MIT’s Department of Materials Science and Engineering, was published in Nature Electronics. This paper presents a significant milestone in TFET development by introducing vertical nanowire tunneling transistors based on the GaSb/InAs heterojunction system.

Research Design and Experimental Procedures

1. Device Design and Fabrication

Using molecular beam epitaxy (MBE), the research team developed highly strained ultrathin heterostructures of gallium antimonide (GaSb) and indium arsenide (InAs). Vertical nanowires with diameters as small as 6 nm were fabricated on the wafer by chlorine-based dry etching and selective wet etching. To investigate the effects of extreme quantum confinement, the InAs section diameter was further scaled down to 5 nm, and an interface-pinned energy band alignment method was applied to enhance the quantum efficiency at the tunneling junction. This innovative design significantly reduced the transistor footprint while suppressing short-channel effects.

The team first created Esaki diodes to characterize the electrical behavior of the tunneling junction, which laid the theoretical groundwork for later designs. The three-terminal heterojunction tunneling transistors were then fabricated using a gate-all-around (GAA) configuration.

2. Device Performance Testing

Through scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS), the researchers verified the atomic-scale smoothness and low defect density at the material interface. Tilt-angle scanning electron microscopy (SEM) was used to monitor nanowire sizes and ensure precise control of dimensions.

Electrical tests measured device performance metrics such as current density, subthreshold swing, and peak transconductance. For example, Esaki diodes with a 5 nm diameter achieved a peak tunneling current density of 3.6 mA/cm² (peak-to-valley current ratio of 6.4) while maintaining exceptional sub-thermal characteristics over a wide current range.

3. Theoretical Modeling and Quantum Simulations

To corroborate experimental results, the team combined first-principles density functional theory (DFT) calculations and quantum transport simulations to interpret how extreme quantum confinement regulates tunneling currents. Thanks to the interface-pinned band alignment method, extreme quantum confinement did not decrease tunneling current as conventional predictions would suggest; rather, it enhanced current density due to an increased electron effective mass and higher density of states (DOS) in the conduction band.

Results and Key Findings

  1. High-Performance Tunneling Transistors: The vertical nanowire tunneling transistor designed by the team achieved a drive current of 300 µA/µm with a 6 nm diameter nanowire. Furthermore, it demonstrated a subthreshold swing as low as 50 mV/dec, breaking the “Boltzmann tyranny” thermal limit of traditional MOSFETs.

  2. Superior Short-Channel Effect Suppression: Experimental models revealed that reducing the vertical nanowire diameter enhances radial electrostatic charge control, effectively suppressing short-channel effects. This improvement not only increased the on-off current ratio (exceeding 10^6) but also significantly boosted the transistor’s on-state transconductance (GM reaching over 1050 µS/µm).

  3. Quantum-Regulated Tunneling Current: Experimental results revealed an unexpected “linear circumferential scaling” of tunneling current when the InAs diameter was reduced below 10 nm. This phenomenon suggests that quantum confinement strengthens tunneling current density, surpassing conventional projections.

  4. Potential for Future Technologies: Benchmark experiments comparing these transistors to Intel’s 10-nm FinFET node showed that the transistors operated at 0.3V with better performance than MOSFETs running at 0.7V.

Conclusion and Significance

By leveraging a broken-band heterostructure and extreme quantum confinement, this study achieves a revolutionary improvement in the performance of tunneling transistors. It demonstrates that quantum confinement effects, when properly managed, can enhance device functionality instead of diminishing it. This work lays the scientific groundwork for “Boltzmann tyranny-free” transistor designs and highlights new opportunities for energy-efficient nanoelectronics. It also offers a promising direction for CMOS technology evolution and underlines the potential of nanoscale heterojunction devices for future computing and IoT applications.