Academic Paper Report: Three-Dimensional Transistors with Two-Dimensional Semiconductors for Future CMOS Scaling

Introduction

In recent years, as silicon-based complementary metal-oxide-semiconductor (CMOS) technology approaches its physical limits, the continued miniaturization and performance optimization of next-generation microelectronics face numerous challenges. The ability to maintain on–off current ratios, increase integration density, and improve energy efficiency at the sub-nanometer scale has become a pressing issue for both academia and industry. Against this backdrop, this paper explores the potential of two-dimensional (2D) transition metal dichalcogenides (TMDs) as critical channel materials in the era beyond silicon CMOS. It also demonstrates the significant potential of new three-dimensional (3D) transistor architectures in sustaining Moore’s Law.

Background and Significance

The continued scaling of CMOS technology has gradually approached its limits, especially for nodes with channel lengths below 15 nm. Traditional silicon-based materials face numerous performance and manufacturing bottlenecks. For example, the larger bandgap and inefficient surface treatment lead to aggravated short-channel effects and deteriorated transport performance. Furthermore, as silicon conductor thickness is reduced to less than 3 nm, there is a significant decline in electron mobility, limiting the scope for efficiency improvements in traditional materials.

2D materials, especially TMDs, with their atomically thin layered structures and excellent intrinsic properties (such as higher mobility and wider bandgap), exhibit potential to overcome these limitations. 2D TMDs can also address issues such as surface roughness scattering and high trap state density. Their superior electrostatic control provides a new pathway for transistor design at sub-10-nanometer nodes. However, the practical application of 2D materials in CMOS technology also requires the development of new 3D device architectures that complement the unique properties of 2D materials.

Paper Source and Author Information

This study was conducted by Arnab Pal, Tanmay Chavan, Jacob Jabbour, Wei Cao, and Kaustav Banerjee, from the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. The article was published in Nature Electronics, Volume 7, December 2024 (Pages 1147–1157) and received for review on October 3, 2023, accepted on October 7, 2024, and officially published online on December 16, 2024.

Research Methodology and Workflow

This study introduced an innovative framework for designing 3D transistors enabled by 2D materials. The framework employs non-equilibrium Green’s function (NEGF) quantum transport simulations combined with density functional theory (DFT) material inputs to comprehensively evaluate the feasibility of 2D materials in 3D transistors.

1. Material Screening and Performance Evaluation

In the material selection phase, the authors compared monolayer (1L), bilayer (2L), and trilayer (3L) samples of different 2D TMD materials (e.g., WSe2, MoS2, WS2). They identified trilayer tungsten disulfide (3L WS2) as the optimal channel material due to its favorable carrier injection velocity and reduced source–drain tunneling current, achieving higher on current (Ion) and on/off current ratios (Ion/Ioff).

2. Device Electrical Property Simulations

The study developed a quantum transport simulation framework to accurately evaluate the current and capacitance characteristics of 2D material transistors. The framework comprehensively considered multi-valley effective masses, non-ideal Schottky contact effects, dimensional scaling effects, and parasitic fields. Using Synopsys Sentaurus and Quantum ATK, the authors modeled device performance and evaluated real-world circuit performance improvements by simulating a 15-stage ring oscillator circuit.

3. Novel 3D Transistor Architecture Design

The study proposed two novel 3D transistor architectures:

• Nanosheet FET (NSFET): By employing 3D gate-all-around (GAA) control, 2D TMDs were used in vertically stacked transistors. This design improves electrostatic performance while reducing device capacitance, thereby enhancing energy efficiency.
• Nanofork FET (NFFET): Building upon the nanosheet concept, this architecture optimized lateral layout by sharing isolation oxide between complementary transistors, significantly increasing integration density.
• Nanoplate FET (NPFET): Based on a planar nanosheet stack, the authors introduced lateral stacking of 2D “TMD plates” tied to ultrathin isolation fins. This configuration provided a nearly tenfold increase in carrier capacity and significantly reduced lateral footprint area.

4. Device Optimization and Circuit-Level Simulation

The study quantitatively analyzed the impact of various key device parameters (e.g., gate oxide thickness, nanosheet width, and contact resistance) on performance. By comparing the transistor characteristics, transconductance frequency, and subthreshold slope of 2D and silicon-based devices, the authors highlighted the substantial advantages of 3L WS2 designs at sub-5 nm channel lengths.

Key Findings and Conclusions

1. Superiority of 3L WS2

In-depth evaluations of 3L WS2 transistors revealed their advantages in both low-standby-power (LSTP) and high-performance (HP) modes. Compared to 8 nm silicon counterparts, 3L WS2 achieved up to a 55% improvement in energy-delay product (EDP) and supported continued CMOS scaling below the 5 nm threshold.

2. Higher Integration Density and Efficiency

Nanoplate transistors offered a tenfold enhancement in integration density through their horizontal stacking architecture. The study showed that even in highly heterogeneous 3D structures, 2D nanoplate transistors could drastically reduce unit cell footprint while maintaining high performance.

3. Material and Architecture Synergy

Through careful engineering of 2D materials and addressing contact resistance challenges, the study demonstrated that 3D transistors with 2D materials could achieve theoretical device performance fidelity of up to 98%, validating their strong application potential in next-generation logic and memory technologies.

Highlight Contributions and Impact

• Methodological Innovation: This study was the first to combine quantum transport modeling with precise electronic band structure characterization of 2D materials, quantitatively analyzing transistor performance.
• Architecture Novelty: The nanoplate architecture (NPFET) was first introduced, highlighting significant advantages in high-integration-density applications.
• Practical Relevance: The study closely aligned with industry requirements, following guidelines from the International Roadmap for Devices and Systems (IRDS), providing feasible pathways for implementation.

Future Directions

The study paves the way for the widespread application of 2D materials in next-generation electronics. Its design framework can be extended to other 2D materials and heterogeneous integration structures. With advancements in manufacturing processes, especially in 2D material deposition and surface passivation, 2D transistors are expected to provide novel solutions for artificial intelligence chips, low-power IoT devices, and other domains, opening new avenues for the semiconductor industry.