Report on the Integration of High-κ Gallium Oxide in 2D Transistors

Academic Background

With the continuous advancement in semiconductor technology, 2D materials (such as molybdenum disulfide, MoS₂) are considered promising candidates for next-generation transistor channel materials due to their unique electrical properties and atomic-scale thickness. However, the performance of 2D transistors largely depends on the quality of the gate dielectric layer. Traditional deposition techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), often fail to create uniform dielectrics on 2D surfaces, resulting in poor interface quality and degraded transistor performance. Thus, developing methods for high-quality and ultra-thin dielectric layer formation on 2D materials has become a significant research focus.

Research Origin

This study was conducted by a collaborative team from multiple institutions, including Kongyang Yi, Wen Qin, Yamin Huang, and others. The team represented organizations such as Nanyang Technological University (Singapore), Nanjing University of Aeronautics and Astronautics (China), Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences (China), University of Texas at Austin (USA), and Rice University (USA). The research, published in Nature Electronics in December 2024, is titled “Integration of High-κ Native Oxides of Gallium for Two-Dimensional Transistors.”

Research Workflow and Experimental Methods

1. Gallium Oxide (Ga₂O₃) Fabrication and Integration

The researchers proposed a gallium oxide (Ga₂O₃) fabrication method based on liquid metals. Liquid metals (such as gallium-indium eutectic alloy, e-GaIn) naturally form thin, uniform Ga₂O₃ layers in ambient environments. Using squeeze-printing and surface-tension-driven methods, the team successfully transferred the Ga₂O₃ layer onto molybdenum disulfide (MoS₂).

• Squeeze-Printing Method: A liquid metal droplet is deposited on the target substrate and squeezed to remove the liquid phase, leaving behind a Ga₂O₃ layer.
• Surface-Tension-Driven Method: A liquid metal layer is pressed to a thickness below 1 mm, rapidly cooled into a solid state, and then heated to form large-scale Ga₂O₃.

2. Characterization of Gallium Oxide

The morphology and uniformity of the Ga₂O₃ films were analyzed using atomic force microscopy (AFM) and transmission electron microscopy (TEM). The results showed a layer thickness of approximately 2.7 nm with uniform coverage across a large area. Additionally, chemical composition and valence states were confirmed via X-ray photoelectron spectroscopy (XPS) and energy-dispersive spectroscopy (EDS).

3. Transistor Fabrication

The research team integrated the Ga₂O₃ dielectric layer onto MoS₂ to fabricate top-gate field-effect transistors (FETs). Source, drain, and gate electrodes were created using electron-beam lithography (EBL) and metal deposition techniques. The Ga₂O₃ layer in the source and drain areas was selectively etched to expose the MoS₂ channels.

Key Findings

1. Dielectric Properties of Gallium Oxide

The Ga₂O₃ layer exhibited excellent dielectric properties, with a dielectric constant of approximately 30 and a breakdown field strength near 11 MV/cm. Capacitance-voltage (C-V) measurements showed stable dielectric constants at low frequencies (<100 kHz), confirming its suitability as a high-κ dielectric material.

2. Transistor Performance

MoS₂ transistors with Ga₂O₃ dielectric layers demonstrated outstanding electrical performance: - Subthreshold Swing (SS): As low as 60 mV/dec, approaching the theoretical limit of 59.6 mV/dec. - On/Off Ratio: Exceeded 10⁸. - Gate Leakage Current: Reduced to 4×10⁻⁷ A/cm², effectively negligible.

3. Large-Scale Integration and Logic Circuits

The team also showcased the application of Ga₂O₃ in large-scale integration. Using the surface-tension-driven method, they successfully fabricated an array of 25 top-gate transistors and demonstrated functional inverters, NAND, NOR, AND, and XOR logic gates. These logic gates worked effectively at low voltages (0.5 V), highlighting the potential of Ga₂O₃ for high-density integrated circuits.

Research Significance and Value

This study introduces a novel method for fabricating Ga₂O₃ dielectric layers, addressing the challenge of depositing high-quality dielectrics on 2D materials. By utilizing the natural oxidation process of liquid metals, the team achieved ultra-thin, uniform Ga₂O₃ layers and applied these to 2D transistors, significantly improving their performance. The approach holds not only scientific value but also provides a feasible pathway for cost-effective, large-scale 2D electronic device manufacturing in the future.

Research Highlights

1. Innovative Fabrication Method: The study employs the natural oxidation of liquid metals to realize ultra-thin and uniform Ga₂O₃ layers, avoiding the flaws of conventional deposition techniques.
2. Exceptional Transistor Performance: The MoS₂ transistors with Ga₂O₃ dielectric layers demonstrated near-ideal subthreshold swing and high on/off ratios, showcasing their potential for low-power electronics.
3. Large-Scale Integration Potential: The successful fabrication of logic gates and transistor arrays underscores the scalability of Ga₂O₃ for high-density integrated circuits.

Conclusion

This research illustrates the successful application of liquid metal Ga₂O₃ in 2D transistors, delivering a simple and efficient method for fabricating high-κ dielectric layers. Using squeeze-printing and surface-tension-driven techniques, the team achieved ultra-thin and uniform Ga₂O₃ layers, significantly enhancing the performance of 2D transistors. These findings provide a novel and practical approach to large-scale, cost-effective 2D electronic device fabrication, offering immense scientific and practical value.